Optimized Design Platform for High Speed Digital Filter using Folding Technique

Implementation of DSP system must satisfy the sampling rate constraint and must require less space and power consumption. Thus finding a reasonable solution to optimize design platform using different algorithm is much needed. In this paper an optimized platform is designed by lifetime analysis which is one of the techniques of folding algorithm for minimizing the registers such that synthesizable RTL is obtained. Folding techniques can be used for the synthesis of DSP architecture that can be operated using single or multiple clocks with less number of registers and functional units resulting in an integrated circuit with usage of small silicon area. A technique is presented for computing the minimum number of registers, allocating the data to these registers and obtains synthesizable RTL code for folded architecture.